1. Field of the Invention
Embodiments of the invention relate to a wafer-level-chip-scale package and related method of fabrication. More particularly, embodiments of the invention relate to a relatively thinner and stronger wafer-level-chip-scale package and method of fabrication.
2. Description of the Related Art
The history of integrated circuit devices is characterized by ever increasing integration densities and continuing attempts to reduce their overall size. Wafer-level-chip-scale packages have been developed to produce smaller integrated circuit devices. Unlike other conventional semiconductor packages in which chips are individually packaged after being cut from a fabrication wafer, wafer-level-chip-scale packages are at least partially fabricated on the wafer (i.e., before cutting individual chip dies from the wafer).
FIG. 1 is a sectional view of a conventional wafer-level-chip-scale package 101. Referring to FIG. 1, wafer-level-chip-scale package 101 includes a semiconductor substrate 111 and a plurality of solder balls 131 formed on a surface of semiconductor substrate 111.
An integrated circuit 121 may have been previously formed on semiconductor substrate 111 and is electrically connected to solder balls 131. Solder balls 131 are bonded to an external device (not shown), thereby allowing the external device to exchange electrical signals with integrated circuit 121 through an electrical connection provided through solder balls 131.
In the conventional wafer-level-chip-scale package 101, a bottom surface 111a and side surfaces 111b of semiconductor substrate 111 are exposed to the surrounding environment. Hence, bottom surface 111a, side surfaces 111b, and/or edges 111c of semiconductor substrate 111 may be broken by an external impact. In addition, when a constituent wafer is ultimately cut into separate wafer-level-chip-scale packages, wafer-level-chip-scale package 101 may be cracked by the cutting process. Such cracking often causes significant damage to the circuit formed on semiconductor substrate 111 and providing the functional capabilities of wafer-level-chip-scale package 101.
Semiconductor substrate 111 is most commonly formed from silicon, or a silicon based material. Silicon based materials are relatively easy to fracture. So, when wafer-level-chip-scale package 101 is formed too thinly, it is particularly easy to fracture. Thus, conventionally, there have been some very strict limits on the practical thinnest with which wafer-level-chip-scale package 101 may be formed.